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Honored Contributor
Honored ContributorLVDS Sampling Data
Hi all, I have on my board double data rate (DDR) LVDS bus samped by clock of 168Mhz. I sampled the LVDS bus using ALTDDIO mega function. The problem is that i have skew between clock and data...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The only true difference is that derive_clock_uncertainty will derive different uncertainties between a virtual/external clock and internal clock. Right now it derives uncertainty to the same clock, which will be less. It's probably going to be a 10ps difference, but true. --- Quote End --- But if you use the incoming clock to e.g. clock the data into a fifo, it is the same clock (externally and internally). If the difference of 10 ps is valid, shouldn't the 'derive_clock_uncertainty' be fixed? --- Quote Start --- I like the virtual clock for multiple reasons. You can use it as a tag for report_timing, i.e.: report_timing -setup/-hold -from ext_clk... Will report timing on all of these input paths, without having to describe the ports. It's not a big deal here since the inputs are a bus, but on interfaces with 20 different port names, it helps. --- Quote End --- But wouldn't "report_timing -setup/-hold -from fga_clk" work as well?
