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Honored Contributor
Honored ContributorLVDS Sampling Data
Hi all, I have on my board double data rate (DDR) LVDS bus samped by clock of 168Mhz. I sampled the LVDS bus using ALTDDIO mega function. The problem is that i have skew between clock and data...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- create_clock -period 5.952 -name fpga_clk [get_ports fpga_clk] create_clock -period 5.952 -name ext_clk derive_pll_clocks ;# (Not doing anything, but I assume you have PLLs doing somethign else) derive_clock_uncertainty set_input_delay -clock ext_clk -max 0.5 [get_ports {LVDS_DATA[*]}] set_input_delay -clock ext_clk -min -0.5 [get_ports {LVDS_DATA[*]}] set_input_delay -clock ext_clk -max 0.5 [get_ports {LVDS_DATA[*]}] -clock_fall -add_delay set_input_delay -clock ext_clk -min -0.5 [get_ports {LVDS_DATA[*]}] -clock_fall -add_delay --- Quote End --- You create two clocks: the incoming clock connected to pin fpga_clk, and a second clock not connected to a pin. As they have the same period they fully overlap each other? Can't we do it in one go? like :
create_clock -period 5.952 -name fpga_clk
set_input_delay -clock fpga_clk -max 0.5 }]
set_input_delay -clock fpga_clk -min -0.5 }]
set_input_delay -clock fpga_clk -max 0.5 }] -clock_fall -add_delay
set_input_delay -clock fpga_clk -min -0.5 }] -clock_fall -add_delay
