LVDS Receiver PLL

Hello Shane,

to be true, I'm a bit confused with Quartus behaviour in this point. What I reported in my posting was something, I just tried to understand if clocking LVDS input Fast PLL with single-ended I/O standard would be possible or not. From the manual, it's clear that the clock signal should be originated either from a dedicated clock input or another PLL. With an otherwise unconnected clock input, this resulted in transfoming the clock input to LVDS, as you reported. This also happened in one case with a clock driving other parts of the design. Then I inserted a clock control block instance manually and the existing clock remains untouched. Quartus issued a warning about the PLL not clocked by an dedicated input but was willing to fit the design.

But this was only an arbitrary test case, I'm not sure about all factors that caused the said result. Now I was aware, that the design I'm just working on, has basically a similar clocking scheme. I have a "main" clock, driven from a single ended input, using a PLL etc. A LVDS receiver part had been planned to use an external LVDS input clock. Cause this external clock is actually a backfeeded derived main clock, I connected the main clock input internally to LVDS receiver block instead, and it works. Probably I could also use a PLL generated clock, but the consideration was not cascading PLLs if unnecessary. The LVDS receiver is standard Megawizard generated with "internal" PLL, just for convenience.

Actually, this is an Arria rather than an Stratix II design, but clock networks are allmost identical between both devices. It seems to me, that there is no difference using V7.1 or V7.2, I got identical behaviour in this respect with both Quartus II versions.

As a conclusion: Quartus, at least, seems to be able to use an single-ended clock input to a clock network already existing in the design as LVDS receiver clock without transforming the I/O standard unasked. Possibly, additional conditions must be met to achieve this.

Regards,

Frank