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Altera_Forum
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18 years ago

LVDS Receiver PLL

I am using using a Stratix II with Quartus 7.1 SP1. When using an LVDS receiver the fitter automatically assigns the input clock as LVDS as well. How would I clock the LVDS receiver using singl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Frank,

What version of Quartus are you using? I've tried this on 7.1SP1 and 7.2SP1 and get the same results. I understand that using an LVDS clock is ideal. However, my PCB is already complete and all I have are single ended clocks.

If you know of a way to get clock the LVDS receiver then please take me through it step by step. Currently, when creating a PLL for the LVDS receiver in the MegaWizard Plugin Manager there is a checkbox for "set-up PLL in LVDS mode". When I check this the PLL is automatically set to Fast PLL in Normal Mode. The other options are ghosted. As you stated in your previous post the PLL should be in "normal feedback mode". I believe that I have achieved this and yet the fitter continues to cry about the "same I/O standard" and automatically assigns the clock to LVDS.

Please advise.

Thanks,

Shane