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Honored Contributor
Honored ContributorLVDS Receiver PLL
I am using using a Stratix II with Quartus 7.1 SP1. When using an LVDS receiver the fitter automatically assigns the input clock as LVDS as well. How would I clock the LVDS receiver using singl...
Altera_ForumHonored Contributor
Honored ContributorHello,
following the Stratix II manual, single-ended IO-standards as LVCMOS should be able to clock Fast PLLs. The restrictions applied by the fitter seems to be beyond device specification and thus a misbehaviour to be corrected. I was able to connect a global clock driving other parts of the design to Fast PLL input - with the aid of a clock control block instance. Apart from what is allowed in the manual, it may be meaningful to use a differential standard anyway. Probably a pseudo LVDS signal made by resistive dividing of a LVCMOS clock is less sensitive to ground bounce than a ground referenced clock. At best use a real LVDS driver, e. g. a single gate SN65LVDS1. Regards, Frank
