Forum Discussion
MK_ABQ
Contributor
ContributorLVDS pin detail on Arria 10
Hi, I am using Arria 10 FPGA in one of our project. OPN: 10AX066N2F40E1HG. I see that Bank 3D is dedicated to LVDS ( picture below from HW schematic). But, my FPGA pin planner says the pin ...
Hi,
LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. So you can use for single-ended.
If that IO you're using for LVDS SERDES, I don't think you can use 1.8V check this SERDES I/O Standards Support in Arria® 10 Devices https://www.intel.com/content/www/us/en/docs/programmable/683461/current/serdes-i-o-standards-support-in-devices.html
Thanks,
Regards,
Sheng
FvM
Super Contributor
Super ContributorHi,
selected IO standard is never ignored. If it's not supported, the design won't fit.
What is driven by respective inputs? Some IP, e.g. SERDES TX doesn't support other IO standards than LVDS with Arria 10 or Cyclone 10 GX. But I'm not sure about SERDES RX.
Regards
Frank
selected IO standard is never ignored. If it's not supported, the design won't fit.
What is driven by respective inputs? Some IP, e.g. SERDES TX doesn't support other IO standards than LVDS with Arria 10 or Cyclone 10 GX. But I'm not sure about SERDES RX.
Regards
Frank
