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Honored Contributor
Honored ContributorLVDS mega function implementation in Cyclone III
iam trying to implement LVDS TX by connecting inputs from VIP clocked video output . requirement is to generate 3 LVDS channels for R,G , B and a differential clock signal . How to implement differen...
Altera_ForumHonored Contributor
Honored ContributorTo output a PLL generated clock, you'll use a dedicated clockout pin pair for lowest jitter and delay skew. Otherwise any differential pair can be used. Connect the non-inverted pin to the clock signal and assign a LVDS or LVDS_3R IO standard (depending on what's supported by the respective pin pair).
