Essentially, you're right. However, to expand slightly...
Max V CPLDs support an 'Emulated LVDS Output Standard'. By driving an external resistor network, along with a further resistor at the input of the remote LVDS receiver, they can support LVDS links.
They do not support LVDS directly on their input pins in the same way various FPGA families do. If you want to drive LVDS signals into a MAX V CPLD you will need an external LVDS receiver.
Refer to application note 636 for more information:
http://www.altera.co.uk/literature/an/an636.pdf (
http://www.altera.co.uk/literature/an/an636.pdf)
Regards,
Alex