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Altera_Forum
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12 years ago

LVDS clock input issue and sdc understanding

Hi there,

i'm working on a project with a Cyclon III (EP3C5), I'm continuing the project and some files are allready done, but it's high level user made and the creator is not available for questions.

I have an LVDS input clock comming from a custom made ASIC, that feeds a PLL in the next way:

I insert the CLK_DIFF & CLK_DIFF_N to an IP ALTIOBUF to convert to single and then insert the output to the PLL. (is this the best solution?)

And the big question, the project has a user made sdc file which I don't completly understand. 

#  Constrain clock port clk with a 16-ns requirement
create_clock -name MAIN -period 16.667 
create_clock -name TDC_CK -period 5 
create_generated_clock -name MAINPLL -source  -multiply_by 1 -divide_by 1 ]
#  Automatically apply a generate clock on the output of phase-locked loops (PLLs)#  This command can be safely left in the SDC even if no PLLs exist in the design# derive_pll_clocks#  Constrain the input I/O path
set_clock_uncertainty 0.2ns -to MAIN
set_clock_uncertainty 0.2ns -to MAINPLL
set_clock_uncertainty 0.2ns -from MAINPLL

why there is only reference to CLK_DIFF?

the TDC_CK name what references? I tried searching for this name all over quartus but I didn't find nothing called TDC_CK. where I suppose to find it?

https://www.alteraforum.com/forum/attachment.php?attachmentid=8135

thanks,

Guillermo

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    "I insert the CLK_DIFF & CLK_DIFF_N to an IP ALTIOBUF to convert to single and then insert the output to the PLL. (is this the best solution?)"

    You can do that.

    Nowadays, in Altera land, nobody bothers: you can simply have just a signal called "CLK_DIFF", connect it to the PLL and declare "CLK_DIFF" to be LVDS in the pin assignment editor. The tool will then automatically create and plate the complementary "CLK_DIFF(n)" signal.

    Regarding the .SDC,

    a) you only need to reference the positive signal of a differential pair.

    b) "TDC_CK" is just the name the author of the .SDC file chose to give the clock which is received on the "CLK_DIFF" pin.

    c) that create_generated_clock is in disagreement with the schematic you've shown; the schematic shows pll_1 being fed by the clock from CLK_DIFF; the .SDC describes pll_1 being fed the clock from CLK_USB

    d) if you use derive_pll_clocks, which you should, don't add create_generated_clock constraints for PLL output clocks.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    thanks rbugalho,

    now I have another problem with sdc file,

    my clock input of 200Mhz is not always available, so when it's not I would like to created from the USB clock (60Mhz).

    Cyclone III PLL does not support PLL with 2 inputs(60 & 200) for creating 1 output(200) so I try what you can see on the next image:

    so I divided in 2 cascade connected PLL, first I try was a MUX but I didn't know how to do the autoswitching when no 200M clock.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8146

    I tried to use the timequest time wizard wich generate the next: 

    
#  Clock constraints
create_clock -name "CLK_USB" -period 16.667ns 
create_clock -name "CLK_DIFF" -period 5.000ns 
#  Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
#  Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

    but I get the following clock warnings: 

    
Warning (15055): PLL "SW_PLL:SW_PLL_inst|altpll:altpll_component|SW_PLL_altpll:auto_generated|pll1" input clock inclk is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
	Info (15024): Input port INCLK of node "SW_PLL:SW_PLL_inst|altpll:altpll_component|SW_PLL_altpll:auto_generated|pll1" is driven by usbclk_pll:USB_CLK_pll|altpll:altpll_component|usbclk_pll_altpll:auto_generated|wire_pll1_clk~clkctrl which is OUTCLK output port of Clock control block type node usbclk_pll:USB_CLK_pll|altpll:altpll_component|usbclk_pll_altpll:auto_generated|wire_pll1_clk~clkctrl

    why is not fed by a dedicated input? I understand that means clk is not using clk dedicated path.

    jitter is a problem for my purpose.

    Also, I would be interested to do sdc file manually like the one I posted first time, I've tried some modifications but I don't know how to declare the new PLL.

    I've been looking for sdc tutorial but they are really messy.

    Thanks,