LVDS clock input issue and sdc understanding

thanks rbugalho,

now I have another problem with sdc file,

my clock input of 200Mhz is not always available, so when it's not I would like to created from the USB clock (60Mhz).

Cyclone III PLL does not support PLL with 2 inputs(60 & 200) for creating 1 output(200) so I try what you can see on the next image:

so I divided in 2 cascade connected PLL, first I try was a MUX but I didn't know how to do the autoswitching when no 200M clock.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8146

I tried to use the timequest time wizard wich generate the next:

#  Clock constraints
create_clock -name "CLK_USB" -period 16.667ns 
create_clock -name "CLK_DIFF" -period 5.000ns 
#  Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
#  Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

but I get the following clock warnings:

Warning (15055): PLL "SW_PLL:SW_PLL_inst|altpll:altpll_component|SW_PLL_altpll:auto_generated|pll1" input clock inclk is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
	Info (15024): Input port INCLK of node "SW_PLL:SW_PLL_inst|altpll:altpll_component|SW_PLL_altpll:auto_generated|pll1" is driven by usbclk_pll:USB_CLK_pll|altpll:altpll_component|usbclk_pll_altpll:auto_generated|wire_pll1_clk~clkctrl which is OUTCLK output port of Clock control block type node usbclk_pll:USB_CLK_pll|altpll:altpll_component|usbclk_pll_altpll:auto_generated|wire_pll1_clk~clkctrl

why is not fed by a dedicated input? I understand that means clk is not using clk dedicated path.

jitter is a problem for my purpose.

Also, I would be interested to do sdc file manually like the one I posted first time, I've tried some modifications but I don't know how to declare the new PLL.

I've been looking for sdc tutorial but they are really messy.

Thanks,