LVDS clock input issue and sdc understanding

"I insert the CLK_DIFF & CLK_DIFF_N to an IP ALTIOBUF to convert to single and then insert the output to the PLL. (is this the best solution?)"

You can do that.

Nowadays, in Altera land, nobody bothers: you can simply have just a signal called "CLK_DIFF", connect it to the PLL and declare "CLK_DIFF" to be LVDS in the pin assignment editor. The tool will then automatically create and plate the complementary "CLK_DIFF(n)" signal.

Regarding the .SDC,

a) you only need to reference the positive signal of a differential pair.

b) "TDC_CK" is just the name the author of the .SDC file chose to give the clock which is received on the "CLK_DIFF" pin.

c) that create_generated_clock is in disagreement with the schematic you've shown; the schematic shows pll_1 being fed by the clock from CLK_DIFF; the .SDC describes pll_1 being fed the clock from CLK_USB

d) if you use derive_pll_clocks, which you should, don't add create_generated_clock constraints for PLL output clocks.