LUTs vs Logic Elements/Cells

If you want to find out LE/LC ratio then remember there are so many variables before you make any decision.

If you start from vhdl design in both cases then it goes through separate compilers/optimisers/fitters ...etc with some control given to the user.

Even 3rd party compilers are vendor specific.

The best test design might be using commercial IPs in both cases, even then it is hard to narrow down the differences. Netlists are targetted and cannot help.

Apart from LE/LC there are some other differences that add to the study problem such as the various dedicated blocks, PLLs/DLL etc.

And don't forget xilinx uses LUTs as memory as well(distributed memory), while altera doesn't as far as I know.