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Hi,
Also if possible is it possible to use convert Logic elements from altera to logic cells in Xilinx. Are there factors that can be used between the respective families?
Basically I am looking for a general approximation of how to interchange between both LUT´s and logic elements and between logic elements and logic cells
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If I can prove that LE = 1.0009 LC then Altera will make me very rich and if LE = 0.9999LC then Xilinx will... This is a very hot contentious market issue.
The answer is very hard and design dependant...Your research will be most valuable source of information for us all.
Honored Contributor
