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Altera_Forum's avatar
Altera_Forum
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17 years ago

LUT to change inputs of another module

Lets say I have two programs in Verilog, one the LUT and the other some logic circuit with a clock. Lets say in that circuit 'a', a1 is an output. a1 is input to the LUT and the output of the LUT is the new clock value for 'a'(clock is an input to 'a'). eg: if a1=2'b00, the LUT changes the clock to 125 khz from 1 MHz.

How could I code this? (just the outlines on how to connect the two programs, integrate the LUT with 'a'. Thanks for any help

Basically I want the LUT to read an output from 'a' and change the clk which is an input to 'a'

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    A wire signal of suitable type is used to connect both modules. 

    wire  awire;
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I am trying to create a multiplication block that uses a slower clock for less processor intensive applications. The slower clock needs to be inputted instantly or very quickly.

    I am not sure what you are suggesting
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I'm not sure what you're asking for. Wiring of modules is shown in any Verilog tutorial, text book or detailed tools manual. If you are asking for something specific, you should clarify.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    I am trying to create a multiplication block that uses a slower clock for less processor intensive applications. The slower clock needs to be inputted instantly or very quickly.

    I am not sure what you are suggesting

    --- Quote End ---

    Hi,

    If i am interpreting your problem correctly, then may be you can instantiate your LUT and multiplication, both modules in one main module.

    and can connect the output of LUT and input to the clock generator module, which in turn generate a new clock and pass on to the multiplication module.

    So as soon as the LUT will generate output, your multiplication module will recieve a new clock.

    e.g. in main_module.v

    {

    wire [2:0]out_clock_value;

    wire out_clock;

    LUT LUT_inst(.input(index), .output(out_clock_value));

    CLK_GEN CLK_GEN_inst(.input(out_clock_value), .output(out_clk));

    MULTIPLICATION MUL_inst( .clk (out_clock), .a(a), .b(b), .answer(answer) );

    }