Altera_ForumHonored Contributor17 years agoLUT to change inputs of another module Lets say I have two programs in Verilog, one the LUT and the other some logic circuit with a clock. Lets say in that circuit 'a', a1 is an output. a1 is input to the LUT and the output of the LUT is ...Show More
Altera_ForumHonored Contributor17 years agoA wire signal of suitable type is used to connect both modules. wire awire;
Recent Discussions5AGXFB7K4F40C5GCyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsQuartus and power domainMCD of AGFA006R16A2E3EPower-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices