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Altera_Forum's avatar
Altera_Forum
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12 years ago

LPM_ROM, I am a newbie please help.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY lpm;

USE lpm.lpm_components.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY LPM_ROM_MEGAFUNCTION IS

PORT( A_address :IN std_logic_vector (7 downto 0);

Sclk :IN std_logic;

Data :OUT STD_LOGIC_VECTOR (0 DOWNTO 0));

END LPM_ROM_MEGAFUNCTION;

Architecture Behavioural of LPM_ROM_MEGAFUNCTION is

component Variation1

PORT

(

address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

clken : IN STD_LOGIC := '1';

clock : IN STD_LOGIC := '1';

q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

end component;

--SIGNAL Signal_1, Signal_2, Signal_3 :std_logic;

BEGIN

address => A_address,

clock => Sclk,

q => Data

End Behavioural;

=============>GIVES THE FOLLOWING ERROR MESSAGE<================== Info: *******************************************************************

Info: Running Quartus II Analysis & Synthesis

Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition

Info: Processing started: Fri Nov 01 19:54:35 2013

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LPM_ROM_MEGAFUNCTION -c LPM_ROM_MEGAFUNCTION

Info: Found 2 design units, including 1 entities, in source file variation1.vhd

Info: Found design unit 1: variation1-SYN

Info: Found entity 1: Variation1

Error (10500): VHDL syntax error at LPM_ROM_MEGAFUNCTION.vhd(29) near text "=>"; expecting "(", or "'", or "."

Info: Found 0 design units, including 0 entities, in source file lpm_rom_megafunction.vhd

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Peak virtual memory: 239 megabytes

Error: Processing ended: Fri Nov 01 19:54:36 2013

Error: Elapsed time: 00:00:01

Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The rom instantiation is wrong:

    LIBRARY ieee;

    USE ieee.std_logic_1164.all;

    LIBRARY lpm;

    USE lpm.lpm_components.all;

    LIBRARY altera_mf;

    USE altera_mf.all;

    ENTITY LPM_ROM_MEGAFUNCTION IS

    PORT( A_address :IN std_logic_vector (7 downto 0);

    Sclk :IN std_logic;

    Data :OUT STD_LOGIC_VECTOR (0 DOWNTO 0));

    END LPM_ROM_MEGAFUNCTION;

    Architecture Behavioural of LPM_ROM_MEGAFUNCTION is

    component Variation1

    PORT

    (

    address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

    clken : IN STD_LOGIC := '1';

    clock : IN STD_LOGIC := '1';

    q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

    );

    end component;

    --SIGNAL Signal_1, Signal_2, Signal_3 :std_logic;

    BEGIN

    rom_unit : variation1

    port map

    (

    address => a_address,

    clken => '1',

    clock => sclk,

    q => data

    );

    End Behavioural;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --Look at this....

    --You need the PORT MAP after the begin. I am not sure this will work for you

    --but it is definitely closer.

    LIBRARY ieee;

    USE ieee.std_logic_1164.all;

    LIBRARY lpm;

    USE lpm.lpm_components.all;

    LIBRARY altera_mf;

    USE altera_mf.all;

    ENTITY LPM_ROM_MEGAFUNCTION IS

    PORT( A_address :IN std_logic_vector (7 downto 0);

    Sclk :IN std_logic;

    Data :OUT STD_LOGIC_VECTOR (0 DOWNTO 0));

    END LPM_ROM_MEGAFUNCTION;

    Architecture Behavioural of LPM_ROM_MEGAFUNCTION is

    component Variation1

    PORT (

    address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

    clken : IN STD_LOGIC := '1';

    clock : IN STD_LOGIC := '1';

    q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

    );

    end component;

    --SIGNAL Signal_1, Signal_2, Signal_3 :std_logic;

    BEGIN

    --address => A_address,

    --clock => Sclk,

    --q => Data

    THE_COMPONENT_YOU_WANT: Variation1

    PORT MAP ( address => A_address,

    clock => Sclk,

    q => Data

    );

    End Behavioural;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Perfect.... I spent three hours today writing it left right and centre again and again. But no Joy.

    (Level of Happiness right now is 1000000000000%)

    Thank You

    Thank You

    Thank You

    Thank You

    Thank You

    Thank You
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    It compiled in first go, I would love to become Altera Guru like you guys :D

    Thank you Both :) yet again Jasper4 & Bertulus.

    I will be on this forum a lot now lol in Gurus company.