Forum Discussion
FvM
Super Contributor
2 years agoHi,
all core registers are reset by power-on reset. Is the respective counter clocked by an external clock already running during power-on or by a PLL generated clock? In the former case, it's likely to get inconsistent random counter values because POR isn't released synchronously. In the latter case, counter will hopefully start from zero after PLL clock start. If the counter isn't directly driven from a clk but internal logic, things are more complicated.
Generally, use synchronously released reset for all registers to avoid similar problems.
Regards
Frank
yuxi1111
New Contributor
2 years agoAnd there are also many products that have not have problems .