New Contributor
Super ContributorHi,
all core registers are reset by power-on reset. Is the respective counter clocked by an external clock already running during power-on or by a PLL generated clock? In the former case, it's likely to get inconsistent random counter values because POR isn't released synchronously. In the latter case, counter will hopefully start from zero after PLL clock start. If the counter isn't directly driven from a clk but internal logic, things are more complicated.
Generally, use synchronously released reset for all registers to avoid similar problems.
Regards
Frank
New ContributorThanks for your reply! my clock is an external clock. I would like to ask whether the probability of the occurrence of random value will increase with the increase of the use time of the product? Because there was no problem in the beginning, it took a few years before there was a problem. The probability of problems after replacing the chip in the later experiment is greatly reduced.
New ContributorAnd there are also many products that have not have problems .
