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Altera_Forum's avatar
Altera_Forum
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11 years ago

LPM_ADD_SUB result right-shifted on Arria V

I created an lpm_add_sub megafunction using Quartus 13.1 to add two 16-bit unsigned numbers. In ModelSim, everything works as expected. I put X"0001" on both inputs and get X"0002". However once I try the same test on an Arria V GX FPGA, I get X"0001" out. My tests seem to show that the output sum is right-shifted by a bit. Any ideas about what could be wrong?

Megawizard initiated the lpm_add_sub as follows. The clock is 100Mhz and Quartus does not indicate any timing issues. aclr is held at 0 and clken is held at 1 for my tests. 

 LPM_ADD_SUB_component : LPM_ADD_SUB        GENERIC MAP (
                lpm_direction => "ADD",
                lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
                lpm_pipeline => 1,
                lpm_representation => "UNSIGNED",
                lpm_type => "LPM_ADD_SUB",
                lpm_width => 16
        )
        PORT MAP (
                aclr => aclr,
                clock => clock,
                datab => datab,
                clken => clken,
                dataa => dataa,
                overflow => sub_wire0,
                result => sub_wire1
        );

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    THe LPM add sub is widely used and has been around for many years. I suspect it's more likely user error. Have you tried simulating your design?

    can you post some code up for test.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I have tried simulating by design in ModelSim (Altera edition). Everything worked fine there. These problems only turn up once I start doing tests on the board.

    The code that I have to test this on the board is very simple: 

    TFCALC: lpm_add_sub_16
    port map (
      aclr      => '0',
      clken     => '1',
      clock     => clock_100MHz,
      dataa     => vme_register_4rd(15 downto  0),
      datab     => vme_register_4rd(31 downto 16),
      overflow  => tf_calc(16),
      result    => tf_calc(15 downto 0)
    );

    vme_register_4rd is a 32-bit register that I can write to using VME. This allows me to try adding different values without having to recompile. tf_calc is a read-only VME register, which I read from the single-board computer to see the output of the result. I have attached the VHDL file created by megawizard for the lpm_add_sub_16 entity.

    I have also added SignalTap on all ports on the lpm_add_sub_16 block to make sure that they are being set correctly. As you can see in the attached screenshot, they are set correctly.

    Please let me know if there are any other files from my Quartus project that I should include.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    that does seem a little odd.

    If you are sure it is not user error - try raising a mysupport request?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Strange but true, I see the same issue with LPM_ADD_SUB in my Arria V design. In Modelsim, everything works.

    Any chance that kkrizka is still around and knows what the cause was?