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Altera_Forum
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11 years ago

LPM_ADD_SUB result right-shifted on Arria V

I created an lpm_add_sub megafunction using Quartus 13.1 to add two 16-bit unsigned numbers. In ModelSim, everything works as expected. I put X"0001" on both inputs and get X"0002". However once I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I have tried simulating by design in ModelSim (Altera edition). Everything worked fine there. These problems only turn up once I start doing tests on the board.

The code that I have to test this on the board is very simple: 

TFCALC: lpm_add_sub_16
    port map (
      aclr      => '0',
      clken     => '1',
      clock     => clock_100MHz,
      dataa     => vme_register_4rd(15 downto  0),
      datab     => vme_register_4rd(31 downto 16),
      overflow  => tf_calc(16),
      result    => tf_calc(15 downto 0)
    );

vme_register_4rd is a 32-bit register that I can write to using VME. This allows me to try adding different values without having to recompile. tf_calc is a read-only VME register, which I read from the single-board computer to see the output of the result. I have attached the VHDL file created by megawizard for the lpm_add_sub_16 entity.

I have also added SignalTap on all ports on the lpm_add_sub_16 block to make sure that they are being set correctly. As you can see in the attached screenshot, they are set correctly.

Please let me know if there are any other files from my Quartus project that I should include.