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MSe's avatar
MSe
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2 years ago

LP-HCSL Clock Buffer Output on a Dedicated Clock Input Pin - Arria 10 GX 160

Dear Intel Support Team, I am having some trouble designing my LP-HCSL Clock Signal to a Dedicated Clock Input, with regard to the available standards. My setup: Intel FPGA 23.2.0.94 Pro Edition...
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FvM's avatar
FvM
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2 years ago

Hi,

my suggestion is, make it simple. A10 LVDS input can receive HCSL clock at 100 MHz directly due to wide common mode range. There's no 85 ohm differential termination, but it's not necessarily required.

MSe's avatar
MSe
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2 years ago

Thanks @FvM for your feedback.

You are reading my mind, keeping it simple is exactly where I wanna go.

So setting an OCT=85R with or without calibration is not possible,

also the Receiver Rx OCT is just for the ACVR Banks, not for the I/O Banks.

Leaves me to just one choice, switching the LVDS Input Termination to OFF,

and placing a 85R or rather 84.5R close to the clk_ pins.

I hope by switching the termination to Off, it doesn't mess with the DC biasing.

Regards

Marcel