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The two clocks are not synchronised, but are guarenteed to be very very close in frequency, such that a pre-cal to ascertain the phase offset will allow the two to run in phase for a reasonable length of time without phase slip (a few milli seconds at least, which is enough).. the biggest problem will not be drift, but low frequency phase jitter, and that's what worries me.
The 'tester' is like nothing what normally sits on a bench, we're using an LTX Cedance Diamond series tester.
All these sorts of testers demand to be 'clock master' to anything they are testing, but their clocks are not RF-capable and they cannot accept an external clock, so we need to cope with two very slowly drifting clocks, so the chip will be locked to an RF-clean clock not the tester clock, but the tester will still want to be 'clock master'. A FIFO gives us a solution whereby we need no guesswork.. it should 'just work'...:rolleyes:
Anyway, many thanks for your time and effort.
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Ok, thanks for the explanation. A FIFO-based solution will meet your requirements. The FIFO full/empty signals can be monitored to catch any excessive phase drifts. Look at the Cyclone IV series devices.
Cheers,
Dave
Honored Contributor
