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"3 lots"? 3 channels?
How many bits is each 80Msps data stream, eg., (8-bits plus clock) x 3 channels = 24-bits input + 3 input clocks
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4 wires: 80MHz clock, 3x 80Msps datastreams, datastream1 = 4MSBs of channelA, then 4MSBs of channelB. datastream2 = 4MediumSBs of channelA, then 4MediumSBs of channelB. datastream3 = 4LSBs of channelA, then 4LSBs of channelB, having clocked out 8bits on each datastream the whole thing repeats. There is no 'latch' all timing is dead reckoned off a starting pattern. (yuk)
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What logic levels? 2.5V LVCMOS, LVDS, CML, etc?
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1.8V CMOS. (I believe.. silicon is still in development but nealy done)
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Mashed up in what way? If its just the ordering of bits that is weird, an FPGA does not care. If the data is XOR modulated or 8/10B encoded, then the FPGA can decode.
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not xored etc. I know the FPGA shouldn't care but it will need sorting out inside the FPGA as the kit that follows does care.
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Why a FIFO? Do you want the data output in a single clock domain? If so, are the three input clocks phase-locked, but arbitrarily skewed?
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The problem is the tester clock that the data has to be aligned too is not good enough to drive the RF, so we are forced to have two asynchronous clocks, they are almost phase locked, so even with thousands of samples we
shouldn't get even one clock cycle drift. Trouble is "shouldn't" isn't "doesn't" and we can't afford to assume we won't get a problem... not if it risks bakcing up 10s of thousands of product chips.
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"Extracting" in what way?
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The tester needs to be 'bus master' in whatever interface we have between the CPLD/FPGA and the tester. I'm envisioning a 12bit wide databus plus a few control lines, running at 20Msps.
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Cheers,
Dave
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thanks
Mike
Honored Contributor
