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1. data input to device is at 80Msps.. 3 lots plus external Clock.
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"3 lots"? 3 channels?
How many bits is each 80Msps data stream, eg., (8-bits plus clock) x 3 channels = 24-bits input + 3 input clocks
What logic levels? 2.5V LVCMOS, LVDS, CML, etc?
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2. data is all mashed up, so needs untangling, then FIFOing... ideally 24bits wide by 10, more if possible.
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Mashed up in what way? If its just the ordering of bits that is weird, an FPGA does not care. If the data is XOR modulated or 8/10B encoded, then the FPGA can decode.
Why a FIFO? Do you want the data output in a single clock domain? If so, are the three input clocks phase-locked, but arbitrarily skewed?
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3. data then needs extracting on a parallel interface, 12 databits wide, plus a few control bits.
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"Extracting" in what way?
Cheers,
Dave
Honored Contributor
