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Altera_Forum
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15 years ago

Loss of lock in the PLL of ALTLVDS_Rx

Hi, I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and conn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm sorry, but I don't know how can I get information about bandwidth setting of PLL ALTLVDS_Tx and ALTLVDS_Rx.

PLLs of ALTLVDS_Tx and ALTLVDS_Rx are configured as internal (incorporated into ALTLVDS_Tx/Rx) but not external.

Only one PLL (which generates internal clocks for my logic) is accessible to get info about bandwidth. In the section "Bandwidth/SS" of wizard it was configured as "Auto". I set it option to Preset -> "Low" but it didn't help.