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Altera_Forum
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15 years ago

Loss of lock in the PLL of ALTLVDS_Rx

Hi, I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and conn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I tried project with disabled option "Use shared PLL(s) for receivers and transmitters" in both ALTLVDS_Rx and ALTLVDS_Tx. But losses of lock in the PLL still exist.

The problem may be concluded in external clock generator. PDF does not contain info about jitter of GXO-7531, and this generator is rather cheap to be an excellent product.