Loss of lock in the PLL of ALTLVDS_Rx

Dear FvM,

thank you for your help.

Your idea is interesting about "...selected common rx_tx_pll".

I didn't emphasize this option in wizard.

Now, I have disabled option "Use shared PLL(s) for receivers and transmitters" in both ALTLVDS_Rx and ALTLVDS_Tx. And I'll try modified project tomorrow.

About clocking scheme.

External clock generator is connected to pin 90 of EP3C16Q240C8. In Quartus II the signal from pin 90 feeds the main PLL which generates internal clocks for my project. Also, the signal from pin 90 is connected directly to input "tx_inclock" of ALTLVDS_Tx.

As to ALTLVDS_Rx, its input "rx_inclock" is defined as differential (LVDS) and connected to pins DIFFCLK_xx (p and n) of EP3C16Q240C8. Therefore, PLL of ALTLVDS_Rx receives its clocks from another board (i.e. from output "tx_outclock" of ALTLVDS_Tx of another board).