Loss of lock in the PLL of ALTLVDS_Rx

Frequency stability of a crystal oscillator doesn't tell much about it's jitter. Generally, crystal oscillator jitter is very low, except for some programmable oscillators (they may be sold as fixed frequency devices though).

I don't excactly understand your clocking scheme. You are operating the receiver source synchronous, with an external reference clock from the transmitter, why have you selected common rx_tx_pll?

I think, the discrepancy with outclock_divide is due to the fact that actual LVDS fast clock frequency is only half the output bit rate, and no bug.