Loss of lock in the PLL of ALTLVDS_Rx

The PLL settings of ALTLVDS_Tx are follows (taken from report of compilation):

Info: Instantiated megafunction "altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component" with the following parameter:

Info: Parameter "common_rx_tx_pll" = "ON"

Info: Parameter "deserialization_factor" = "8"

Info: Parameter "implement_in_les" = "ON"

Info: Parameter "inclock_data_alignment" = "UNUSED"

Info: Parameter "inclock_period" = "50000"

Info: Parameter "inclock_phase_shift" = "0"

Info: Parameter "intended_device_family" = "Cyclone III"

Info: Parameter "lpm_type" = "altlvds_tx"

Info: Parameter "number_of_channels" = "1"

Info: Parameter "outclock_alignment" = "UNUSED"

Info: Parameter "outclock_divide_by" = "4"

Info: Parameter "outclock_duty_cycle" = "50"

Info: Parameter "outclock_multiply_by" = "1"

Info: Parameter "outclock_phase_shift" = "0"

Info: Parameter "output_data_rate" = "160"

Info: Parameter "pll_self_reset_on_loss_lock" = "OFF"

Info: Parameter "registered_input" = "TX_CORECLK"

Info: Parameter "use_external_pll" = "OFF"