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Honored Contributor
Honored ContributorLoss of lock in the PLL of ALTLVDS_Rx
Hi, I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and conn...
Altera_ForumHonored Contributor
Honored ContributorThe PLL settings of ALTLVDS_Tx are follows (taken from report of compilation):
Info: Instantiated megafunction "altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component" with the following parameter: Info: Parameter "common_rx_tx_pll" = "ON" Info: Parameter "deserialization_factor" = "8" Info: Parameter "implement_in_les" = "ON" Info: Parameter "inclock_data_alignment" = "UNUSED" Info: Parameter "inclock_period" = "50000" Info: Parameter "inclock_phase_shift" = "0" Info: Parameter "intended_device_family" = "Cyclone III" Info: Parameter "lpm_type" = "altlvds_tx" Info: Parameter "number_of_channels" = "1" Info: Parameter "outclock_alignment" = "UNUSED" Info: Parameter "outclock_divide_by" = "4" Info: Parameter "outclock_duty_cycle" = "50" Info: Parameter "outclock_multiply_by" = "1" Info: Parameter "outclock_phase_shift" = "0" Info: Parameter "output_data_rate" = "160" Info: Parameter "pll_self_reset_on_loss_lock" = "OFF" Info: Parameter "registered_input" = "TX_CORECLK" Info: Parameter "use_external_pll" = "OFF"
