Loss of lock in the PLL of ALTLVDS_Rx

The warning should be irrelevant in my opinion, because delay skew isn't an issue here and particularly not causing locss of lock.

I'm not sure what's forcing the choice of a TX PLL in your design, most likely a dedicated clock output used for the clock signal transmitted to the receiver. Otherwise Quartus would choose the PLL according to the clock input, if the related PLL isn't already assigned in the design. The clock resource matrix can be seen in the device manual.

A PLL clocked by another PLL (as it's the case with the RX PLL) should be set to high bandwidth according to the device manual. I'm not sure if this done by Quartus autmatically, check the PLL settings in the compiler report.