Loss of lock in the PLL of ALTLVDS_Rx

Also, Quartus II posts message after compilation:

Critical Warning: PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_9hi1:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_90".

It may be the possible reason of loss of lock in the PLL of receiver. But Pin 90 is dedicated clock input (CLK14) in EP3C16Q240C8 and I connected external clock generator (20 MHz) to pin 90.

What pin of EP3C16Q240C8 I need to connect external clock generator ?

How can I determine a dedicated (not remote) clock input pin for PLL used in ALTLVDS_Tx?