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Altera_Forum
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15 years ago

Loss of lock in the PLL of ALTLVDS_Rx

Hi, I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and conn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes,

SATA cable consists of two diff pairs. And I use one of them to transmit data and the second pair to transmit clock.

One SATA cable is assigned to transmit from board "A" to board "B". The second SATA cable is assigned to transmit from board "B" to board "A".

Termination is correct, 100 Ohm SMT resistors (for data and clock pairs respectively) at the receiver.

Data rate is 160 Mbps.

Unfortunately, I have no special oscilloscope to view waveform at the receiver. Before production of PCB simulation was made to set impedance of pathes to 50 Ohm.