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Altera_Forum
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15 years ago

Loss of lock in the PLL of ALTLVDS_Rx

Hi, I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and conn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Do I understand right, that you are sending the clock over the second differential pair with the data? Did you provide correct termination for the LVDS signals? Are you able to check level and waveforms at the receiver?