Honored Contributor
Honored ContributorI don't try to comment all obvious design problems. Just two points:
1. You should think of a process as code, that is executed always (in case of combinational code) or for each clock event (in case of clock synchronous process). In synthesizable code, you can't stop a process and wait for an event or schedule of a delay. 2. A loop is a method to create parallel structures, but not a sequence in time. All iterations are executed simultaneously. A typical FPGA solution for the presented problem would use a system clock and synchronize all external signals to this clock. Also an external signal, most likely the pixel clock could be used as clock. If the other signals have defined timing related to pixel clock, the could be used as clock qualifiers, but synchronizing them would create a better defined timing. As a consequence, hsync and vsync would not be processed as independant clocks rather than by synchronous edge detection.
