Yes, this is far from a typical counter:
1) Don't use variables unless you absolutely have to, or absolutely know what you are doing. 99% of code doesn't need them and gets along better without them. (This one is debatable, but I've seen users have far too many problems. Anyway, make that a signal.
2) Don't make it an integer. Integers are defined over an enormous range, when all you want is 5 bits to count to 31. Basically you're making synthesis create a huge structure and rip it down. In this small example it will work, but done over and over makes your code slow. It also opens you up to mistakes where you do a typing error, and suddenly synthesis takes forever because your 5 bit counter is now 32 bits(or whatever the native length of integer is, I forget). Use integer only for things like indices of a loop. So this should probably be std_logic_vector(4 downto 0);, or if you use integer, put a well-defined range onto it.
3) Don't use loops. Again, you can run into infinity like you're doing here. Use a for statement if you must, which is well defined, and in this case don't use either.
4) Have an asynchronous reset. I won't get into it here, but good practice to get into.
5) Don't use a mod unless you're doing math. This is just a counter, c <= c + 1. If you want it to reset early, just check if it is at the value you want to reset at.
6) In Quartus VHDL, go to Edit -> Insert Template -> VHDL -> Full Design -> Arithmetic -> Counter, and then insert the one you want into a blank page. Then make sure you understand everything about this.
I don't mean to pick on the code, but there are just a lot of things that can go wrong with how you're doing it. Make sure you get a at least one VHDL book and start pouring through the examples, and mimic them in your code. (Or search on the web). Good luck.