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Altera_Forum
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11 years ago

Loopback problem in Stratix V GX

In out project we have implemented a Custom PHY transceiver, running in duplex mode at 5120 MHz, and the loop-back is done externally with a fibre. Through the TX link we send 191 bits (6 lanes with ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Regarding the synchronization, we are not using any pattern because the transceiver mega-function allow us to run this way by setting the "Word alignment mode" as "Bit slipping". Surely the RX data is offset and we have to write our own code to search for the header, but this is something that we have to do in any case as the length of our words is greater (128b) than the width of the RX lanes (32b).

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Yes, you will have to write your own synchronization code. Even without synchronization, you should be able to write out the bits in bit-by-bit format and see the serialized bits you sent, it'll just be the parallel output that might be wrong. If you're using SignalTap, you could just pulse the bit-slip control and then trigger to capture a new trace until you see the pattern you were expecting.

Cheers,

Dave