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Altera_Forum
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11 years ago

Loopback problem in Stratix V GX

In out project we have implemented a Custom PHY transceiver, running in duplex mode at 5120 MHz, and the loop-back is done externally with a fibre. Through the TX link we send 191 bits (6 lanes with ...
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Altera_Forum
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11 years ago

Dear Dave,

thank you very much for your suggestions. I'm fixing some problems that I have in the code in order to run a simulation of the whole project. I will post the results.

Regarding the synchronization, we are not using any pattern because the transceiver mega-function allow us to run this way by setting the "Word alignment mode" as "Bit slipping". Surely the RX data is offset and we have to write our own code to search for the header, but this is something that we have to do in any case as the length of our words is greater (128b) than the width of the RX lanes (32b).

Cheers,

Pablo R.