Looking SPI master/slave in verilog sample

Please try to understand the example at

www.fpga4fun.com/spi2.html (http://www.fpga4fun.com/spi2.html)

Are you experienced in ModelSim ?

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Hi there,

Does anybody has a very simple sample of SPI protocol in simulation about master/slave in verilog? Looking for sample how to connect SPI master to SPI slave and verify in modelsim.

Best regards,

Sean

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I'll second the link below for building an SPI slave in Verilog. It's really well written and works quite well. Our SPI implementation is built on top of it with a bit of extra stuff added to deal with crosstalk we are seeing on the SPI bus.

Mark

Thanks.

I'm looking for a complete SPI master/slave verilog code.... A very simple one. I already looked at opencores.org couple of samples... it works, but it seems to complex design.