Looking SPI master/slave in verilog sample

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Hi there,

Does anybody has a very simple sample of SPI protocol in simulation about master/slave in verilog? Looking for sample how to connect SPI master to SPI slave and verify in modelsim.

Best regards,

Sean

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I'll second the link below for building an SPI slave in Verilog. It's really well written and works quite well. Our SPI implementation is built on top of it with a bit of extra stuff added to deal with crosstalk we are seeing on the SPI bus.

Mark