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Altera_Forum's avatar
Altera_Forum
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14 years ago

Looking SPI master/slave in verilog sample

Hi there, Does anybody has a very simple sample of SPI protocol in simulation about master/slave in verilog? Looking for sample how to connect SPI master to SPI slave and verify in modelsim. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks.

I'm looking for a complete SPI master/slave verilog code.... A very simple one. I already looked at opencores.org couple of samples... it works, but it seems to complex design.