Forum Discussion
Occasional ContributorLooking for help on constraint syntax
If I'm reading your document correctly, you're transferring between a 40 MHz clock domain and a 20 MHz clock domain. As such, you need a multicycle timing exception in your .sdc file. Going from a faster to a slower domain usually requires a -start multicycle to select the correct launch edge for the setup and hold analysis:
set_multicycle_path –from SYSCLK –to CLK20MHZSYS_ext –setup –start 2
set_multicycle_path –from SYSCLK –to CLK20MHZSYS_ext –hold –start 1
Super ContributorIf I'm reading your document correctly, you're transferring between a 40 MHz clock domain and a 20 MHz clock domain. As such, you need a multicycle timing exception in your .sdc file. Going from a faster to a slower domain usually requires a -start multicycle to select the correct launch edge for the setup and hold analysis:
set_multicycle_path –from SYSCLK –to CLK20MHZSYS_ext –setup –start 2
set_multicycle_path –from SYSCLK –to CLK20MHZSYS_ext –hold –start 1
GD76The CPLD gets 20MHz clock. The SYSCLK is 20MHz. Not sure where you got the 40MHz from.
