Looking for FPGA that can have FF and shift register that can clock at 1GHz

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Am I reading wrong or one of these FPGA is over $2000?

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Yep, that is the list price.

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If so, that's too high for my design. Is there any older FPGA that can still work for my requirements?

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Yes, there are cheaper devices. As was commented, you can probably use a Cyclone or Arria device.

Before you select a part, you need to determine *what* that part needs to do. You're in the situation of not quite knowing what you want to do, so its really not a problem that you simply start by looking at a data sheet. You're better off reading the data sheet for the device with all the features, and then use Quartus or Modelsim to figure out what you can actually use on that part to achieve your goal, and then try that same logic in a lower-cost device.

For example, lets say you can use LVDS at 1GHz. The Stratix series definitely handles that data rate, but do the Arria and Cyclone series devices? Look at the data sheets for the Arria V and Cyclone V devices and see. Then do the same for the maximum SERDES data rates. Each of these 'rates' will also depend on the speed grade of the part, eg., the lowest speed grades are the lowest cost, and will have the slowest speed. However 'slowest' for a transceiver may be 2.5Gbps ... which could be fast enough for your application ... once you have figured out what the logic needs to do.

So, don't be scared off just yet, consider yourself 'educated' :)

Cheers,

Dave

I am coming up with a new design that need only a few registers that clocked at 1GHz. The only registers that clocked at 1GHz are

1) Divided by 5 counter to get down to a 200MHz clock called CLK+0nS.

2) 4 DFF shift register clocking at 1GHz to shift the 200MHz clock to get CLK+1nS, CLK+2nS, CLK+3nS, CLK+4nS. Each output of the shift register is 200MHz, but each delayed by 1nS.

I use these 5 clocks to capture the input event at 1nS resolution. The rest of the pipeline registers are running at 200MHz only. If it needs to be, I can further demux it down to 100MHz easily.

With this new design, how cheap the FPGA I can use? I only need about 10 of the DFF to run at full 1GHz, the rest are 200MHz only. Please help.

So Far, I read the First 2 chapters of the Stratix V manual, does this help in understanding the older, slower FPGAs? Or should I find the right one for the new design and start over again?

Thanks

As an example of a lower cost device:

Lets find a Cyclone V with transceivers ...

https://www.altera.com/products/fpga/cyclone-series/cyclone-v/features.html

Cyclone V GX FPGAs with 3.125 Gbps transceivers

Click on the "BUY" link and look at the Cyclone V GX devices.

The cheapest "in stock" device is the 5CGXFC3B7F23C8N for $81

http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-2757-nd

What can this part do? Use page 7 of the Overview to decode the part number:

5C Cyclone V

GX 3Gbps transceivers

F 2 PCIe and 2 memory controllers (max)

C3 31.5K LEs

B 3 transceivers

7 2.5Gbps transceiver speed

F23 Package type

C Commercial

8 Slowest speed grade

N RoHS

So this part has three 2.5Gbps transceivers. If you were using transceivers for your interface, it *would not* meet your requirement, since it does not have 16 channels, but if you look at the part number table, the maximum number of transceivers is 12, a single piece of this particular part would not meet your needs anyway.

How about LVDS then? Search in the Overview document for LVDS and you'll see ...

"875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter"

so this part does not support 1Gbps LVDS.

Keep in mind that you could also use an external SERDES ...

http://www.ti.com/ww/en/analog/interface/serdes.shtml

where the external chip samples at 1Gbps performs serial-to-parallel conversion, and then you interface the parallel bits into the FPGA for pattern detection.

This complicates the PCB design, since you've now got to route the parallel bits, but it could make the solution cheaper.

Cheers,

Dave

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I am coming up with a new design that need only a few registers that clocked at 1GHz. The only registers that clocked at 1GHz are

1) Divided by 5 counter to get down to a 200MHz clock called CLK+0nS.

2) 4 DFF shift register clocking at 1GHz to shift the 200MHz clock to get CLK+1nS, CLK+2nS, CLK+3nS, CLK+4nS. Each output of the shift register is 200MHz, but each delayed by 1nS.

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What you are describing here is essentially a PLL and an LVDS SERDES channel.

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With this new design, how cheap the FPGA I can use? I only need about 10 of the DFF to run at full 1GHz, the rest are 200MHz only. Please help.

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You'll need one with LVDS at 1Gbps, or if you can split your comparator/limiting amplifier output into two signals, then you could sample it using two LVDS inputs at 500Mbps, and use the PLL to phase-shift the sampling clocks by 1ns. Basically you'll create two 1-bit ADCs that have their clocks skewed by 1ns.

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So Far, I read the First 2 chapters of the Stratix V manual, does this help in understanding the older, slower FPGAs? Or should I find the right one for the new design and start over again?

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You should determine whether your design can be implemented as a 1-bit sampling system. It would be a shame for you to spend time learning about LVDS deserializers and then realize you need amplitude information from your RF signal. If you do need RF amplitude information, you need to determine the resolution you need.

Cheers,

Dave

I had a quick look at the Arria V, Cyclone V, and MAX 10 data sheets. These devices do not support 1Gbps, but they all appear to support 500Mbps, so you could conceivably use interlaced sampling to achieve 1Gbps sampling. If you look at the link to the Texas Instruments/National Semiconductor SERDES parts, you'll see there are plenty of devices that can operate at 1Gbps, that then deserialize to slower parallel data streams, eg., 1-bit at 1000Mbps to 16-bits at 62.5MHz (LVCMOS logic levels), which is pretty easy to interface to.

Cheers,

Dave

Thanks Dave for guiding me through this difficult times as this is really not my specialties. I have to re-read your 3 posts more.

But I can tell you I don't need analog amplitude information. I just do all amplification and drive through the comparator outside. I just find a comparator that has output format to match the FPGA.

I'll take a look at Ti SERDES and see what works. It would be nice to slow down the data rate so the FPGA is out of the bottle neck. I designed enough with MAX and APEX before, but never really pushing the speed of the device, so I just wrote the AHDL like programming, never worry about the clock path and all. If I can slow down to the point that I don't have to pay special attention to the how the signal path goes, that will be that much better for me. I have no intention to become a FPGA engineer!!! Hell, I retired 10 years already, the former company called me up to do an R&D project two months ago, I just sent out the pcb, and now they just want me to work on this.

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Thanks Dave for guiding me through this difficult times as this is really not my specialties. I have to re-read your 3 posts more.

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I like to help :)

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But I can tell you I don't need analog amplitude information. I just do all amplification and drive through the comparator outside. I just find a comparator that has output format to match the FPGA.

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Good, then all you are after is a 1-bit ADC. Now you have to decide whether 1GHz sample rate is sufficient.

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I'll take a look at Ti SERDES and see what works. It would be nice to slow down the data rate so the FPGA is out of the bottle neck.

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Technically the FPGA is not the bottleneck, since some FPGAs can handle it, but you want to keep the price low, and you don't really need that much FPGA logic.

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I designed enough with MAX and APEX before, but never really pushing the speed of the device, so I just wrote the AHDL like programming, never worry about the clock path and all. If I can slow down to the point that I don't have to pay special attention to the how the signal path goes, that will be that much better for me.

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If you use an external SERDES then you could use a MAX 10 device. They're really just an FPGA with on-chip configuration memory.

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I have no intention to become a FPGA engineer!!!

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Yes, but you are an engineer, and you like solving problems :)

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Hell, I retired 10 years already, the former company called me up to do an R&D project two months ago, I just sent out the pcb, and now they just want me to work on this.

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Good for you :)

I see two reasonable options;

1. Mid-range FPGA sampling at 1GHz using two LVDS inputs and a PLL with interlaced sampling at 500Mbps.

This requires that your comparator output be routed to two FPGA inputs. If your comparator output is LVDS, then you need to find a 1:2 fanout buffer that operates at 1GHz. If an LVDS 1:2 buffer does not exist, then look for an LVPECL or CML comparator and 1:2 fanout.

2. External 1Gbps SERDES with parallel output plus a MAX 10

Cheers,

Dave

Thanks for your detail reply

I did look at the SERDES a little, I don't think that will work. Sounds like SERDES expect a data with constant rate and use PLL to lock onto the input stream. My data is totally random. The average rate is only about 20MHz. BUT because of the randomness, two pulse can be as close as 1nS between adjacent channel. That's the reason I need to have this high speed sampling. Also I cannot do coincident detection with the SERDES.

I have been designing the circuit, looks like the description in post# 33 above still hold. Attrached is the schematic of the front end, I need about:

1) About 7 DFF that HAVE to run at 1GHz clocking.

2)70 DFF run at 200MHz,

3) The rest of the DFF are 100MHz or slower.

4) All adders and logics with propagation delay of 10nS if possible. Or else, more demuxing.

What is the cheapest FPGA family I can use to fulfill this requirement?

Again, thanks for your patience.

Alan

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I did look at the SERDES a little, I don't think that will work. Sounds like SERDES expect a data with constant rate and use PLL to lock onto the input stream. My data is totally random. The average rate is only about 20MHz. BUT because of the randomness, two pulse can be as close as 1nS between adjacent channel. That's the reason I need to have this high speed sampling. Also I cannot do coincident detection with the SERDES.

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Right, you're looking for a very specific SERDES - one that is really just a high-speed shift-register with an *external* reference clock, not a clock and data recovery circuit (or a CDR that can be forced to stay in lock-to-data mode). When I had a quick glance at the TI site, it looked like some of the display-link, channel-link, and FPGA-link devices *might* have had those characteristics, but I didn't have time to look into it in detail :)

Take a look at this page

https://www.ovro.caltech.edu/~dwh/correlator

click on the COBRA Digitizer photo. The big black chips are ECL serial-to-parallel shift-registers doing exactly what you want.

https://www.ovro.caltech.edu/~dwh/correlator/pdf/digmodule_sch_rev_c1.pdf

https://www.ovro.caltech.edu/~dwh/correlator/pdf/digmodule_spec_rev_c1.pdf

The part number is 100E445. Both Micrel and OnSemi make them. The can operate at up to 2Gbps. The COBRA board cascades two of them, so that you create a 1:8 shift register.

This is the type of part you want. I don't think you want to use this exact part. See if you can find an LVPECL equivalent (100EP445), or CML, or LVDS. The point of showing you these parts is to show that what you want to do is possible using external parts.

The COBRA board contains a 1GHz ADC, the ECL logic slows the data down to 125MHz, and then the FPGAs process the data. These are FLEX10K devices ... from 2000. A lifetime ago :)

If you use an external shift-register and get the logic interface levels correct, you can use a low-cost FPGA. But you'll want to make sure your shift-registers are also low cost too :)

NOTE: Mouser has the 100EP445 (4-bit) and 100EP142 (9-bit) shift-registers for about $20 each. If you need 16 channels then you need $320 worth of parts. An FPGA with 500Mbps LVDS interlaced to sample at 1GHz is not a bad option ...

What would be nice is a part like this, but with 1Gbps lanes (rather than eight 112MHz x 6 = 672Mbps lanes)

http://www.ti.com/product/ds90cr482/description

From the Lattice web site: "Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family" (but I could not find that data rate in the datasheet, I only found 400MHz, i.e., 800Mbps).

Cheers,

Dave

Thanks Dave for all your time. I read through your posts again. I looked into the SERDES. I don't see Ti has deserializer with serial input clock. I found Maxim MAX3885 have serial input clock. The 100EP445 actually getting closer, it's simpler without the bit skipping, you just reset the chip to start over. But even if that works out, it's 16 channels of this. I still have to worry about doing reset to synchronize the bit streams of all channel. There's always a chance of getting out of sync and data become garbage.

I forgot to mention, My block diagram schematic is only one of the ten modules in the system. So there will be 160 channels total!!! that's a lot of deserializers!!! The way I design in post# 39 is such that I pack all 16 of the serial bits from the 16 channels into the same register, so each 16bit parallel output of the register is the same bit from each channel. So the bits from all 16 channels are aligned by design.

In my design, I have one counter and five DFF that run at 1GHz. I can use 10EP016 binary counter and 10EP451 Hex DFF. Two ECL to generate a 5phase clock to chop the 200MHz clock into 5 clocks that are 1nS delay from each other. I then can feed the 5 clocks into a FPGA to do all the deserializing. This way, I only have two ECL circuit driving the timing for 16 channels and all 16 channels are processed by one FPGA. sounds like a winner so far. I am going to think about if I can drive all 10 of this circuit(160 channels) with just this two ECL. But that can be challenge as traces are delay lines.

So my question to you if you look at the schematic in post# 39:

1) with the external ECL circuit, I am running 5 of the 200MHz clock into the FPGA. Can the Cyclone V works for me? $81 is acceptable.

2) Is there cheaper FPGA that can work with 5 200MHz clock?

3) I only draw the front end deserializer that spit out 200MHz data, I likely still want to demux out further to slow to at least 50MHz or even 25MHz to lower the power dissipation of the FPGA(CMOS power decrease at switching frequency goes down). Then I have to have a few 14Bit adders, then the read logic from uP. What size FPGA do I need?

Again, thanks for all your time in helping me.

Alan