Looking for FPGA that can have FF and shift register that can clock at 1GHz

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Thanks Dave for all your time.

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You have an interesting problem, so you piqued my interest :)

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I found Maxim MAX3885 have serial input clock.

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This part looks suitable. What didn't you like about it (if anything)? Digikey lists it for $30 each.

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The 100EP445 actually getting closer, it's simpler without the bit skipping, you just reset the chip to start over. But even if that works out, it's 16 channels of this. I still have to worry about doing reset to synchronize the bit streams of all channel. There's always a chance of getting out of sync and data become garbage.

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You only need to reset at power-on, after that point your system would clock the parts at 1GHz and capture the data at 250MHz. The system would be synchronous, and you'd use the FPGA PLL to ensure that you captured the ECL output data in the middle of the 250MHz sampling window. You can easily check this is working by adjusting the phase of the 250MHz clock while sampling a known signal, eg., a sinusoid.

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I forgot to mention, My block diagram schematic is only one of the ten modules in the system. So there will be 160 channels total!!! that's a lot of deserializers!!!

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Nah, its not that many. Check out the photos of the FPGA boards in here ...

https://www.ovro.caltech.edu/~dwh/wbsddc/altera_fpgas_in_radio_astronomy.pdf

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The way I design in post# 39 is such that I pack all 16 of the serial bits from the 16 channels into the same register, so each 16bit parallel output of the register is the same bit from each channel. So the bits from all 16 channels are aligned by design.

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That is fine. What you have shown is pretty trivial by FPGA standards. In the system in the PDF I just linked to, all 120 boards are operating synchronously to a common clock processing multi-Gigahertz of bandwidth. Your proposed system can use pretty much the same ideas. What we have to determine is whether using a Stratix series device with 1Gbps LVDS channels is cost-effective relative to an external SERDES plus a lower-cost FPGA. I suspect the FPGA-only solution will be competitive, since you will have a much simpler PCB design. But there is no need to guess, just analyze and price the various options. The Stratix II devices have LVDS that operate at 1Gbps too, so perhaps an older device would be appropriate.

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In my design, I have one counter and five DFF that run at 1GHz. I can use 10EP016 binary counter and 10EP451 Hex DFF. Two ECL to generate a 5phase clock to chop the 200MHz clock into 5 clocks that are 1nS delay from each other. I then can feed the 5 clocks into a FPGA to do all the deserializing. This way, I only have two ECL circuit driving the timing for 16 channels and all 16 channels are processed by one FPGA. sounds like a winner so far. I am going to think about if I can drive all 10 of this circuit(160 channels) with just this two ECL. But that can be challenge as traces are delay lines.

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Now add up the BOM for these parts, and estimate the cost of the PCB ... Its "only" 1Gbps, so FR4 is fine, but you'll draw a lot of current on the ECL termination rail, or dissipate a bunch of power in the termination resistors. Do the math on what that type of design "costs" and compare it to the FPGA-only solution.

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So my question to you if you look at the schematic in post# 39:

1) with the external ECL circuit, I am running 5 of the 200MHz clock into the FPGA. Can the Cyclone V works for me? $81 is acceptable.

2) Is there cheaper FPGA that can work with 5 200MHz clock?

3) I only draw the front end deserializer that spit out 200MHz data, I likely still want to demux out further to slow to at least 50MHz or even 25MHz to lower the power dissipation of the FPGA(CMOS power decrease at switching frequency goes down). Then I have to have a few 14Bit adders, then the read logic from uP. What size FPGA do I need?

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Before you decide that the FPGA is the overriding cost driver, you need to create a BOM with the ECL parts too. They're pretty expensive parts, and they run really hot. You'll need cooling. Is that acceptable?

In the CARMA boards

https://www.ovro.caltech.edu/~dwh/carma_board/

Look at the diagram on p64 of this doc

https://www.ovro.caltech.edu/~dwh/carma_board/engineering_specification.pdf

The Stratix II FPGAs have 32-bits of LVDS on the left side of the chip going to the front-panel, and 16-bits from the 1GHz digitizer. The part has at least 32-bits on each side of the device. If your RF comparator circuit does not take up much space, then you can potentially get 64 channels per FPGA.

Each of the external deserializer devices we have found are either $20 or $30 each so 64 of the external devices would cost $1280 to $1920. Which is in the price range of several of the Stratix series devices.

I'd recommend pricing out the two options, presenting both options to the people you are working for, and then let them think about which solution they would like you to pursue.

If they give you the go-ahead, then you can build a prototype ...

Cheers

Dave

I am looking for deserializer, I don't think Ti even have a part that can use external serial data clock. Everyone just have the serial data input and use PLL to lock onto the data. so far, other than 100EP455, the only other I can find is MAX3885. If you know of any other ones, please let me know.

Thanks

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I am looking for deserializer, I don't think Ti even have a part that can use external serial data clock. Everyone just have the serial data input and use PLL to lock onto the data. so far, other than 100EP455, the only other I can find is MAX3885. If you know of any other ones, please let me know.

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These are pretty much the same ones that I found too.

You should go and create the VHDL/Verilog to describe the design using 1Gbps LVDS channels. Then create a simulation with a realistic input signal and see if it works ok. There may be something you've missed, and that 1Gbps is not fast enough. If that is the case, then you'd need to look at using the FPGA SERDES channels.

Look in the Arria device overview, there are parts with 36 SERDES transceivers, and their LVDS channels operate at up to 1.6Gbps (the LVDS data rate might be device speed specific - read the data sheet).

Cheers,

Dave

Thanks Dave

I never expect one FPGA can get into thousands of dollars!!! I would like to try $300 or below. I downloaded Arria GX, Arria II and Arria V. which one is better for my application? Of cause I would like to have as many 1GHz SERDES channel as possible.

Anyone of these have Flip Flops that can be clocked at 1GHz? If these don't have it, what is the lowest cost FPGA that has 1GHz flip flop?

Thanks

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Can this one work?

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Sure, lots of them can work, but you need to *STOP* looking at the prices and *IMPLEMENT* a design using the 1Gbps LVDS channels.

Once you have *CONFIRMED* that 1Gbps LVDS works for your application, then you can look at the Arria series devices that support that LVDS rate. They will be lower cost than the SERDES parts.

However, if your simulations with realistic signals feeding into 1Gbps LVDS show you *CANNOT* use 1Gbps, but that you need to use a faster sample rate, then you have to look at using the SERDES devices in lock-to-data (synchronous) mode.

You've got to learn how to use the LVDS IP cores, and then perhaps the SERDES IP cores. Start with the LVDS IP cores, they are easier.

Cheers,

Dave

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I downloaded Arria GX, Arria II and Arria V.

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I have no idea. I have not read the data sheets. I looked at the Arria V data sheet and confirmed that its LVDS operate at 1Gbps. Its up to you to do the work to look at the other data sheets.

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Anyone of these have Flip Flops that can be clocked at 1GHz?

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A 1Gbps LVDS receiver is a serial-to-parallel converter operating at 1GHz clock rate. It is a hard IP block in the FPGA I/O core. But I have already explained that. You should have taken the time to read the Stratix V handbook LVDS section.

Cheers,

Dave

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Thanks, I read the LVDS section first.

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Excellent :)

Then create an instance of the component and try to simulate it. The LVDS IP core User Guide might have a simulation example associated with it.

Yeah, there is, go here

https://www.altera.com/support/literature/lit-ug.html

and scroll down to "LVDS SERDES Transmitter / Receiver (ALTLVDS_TX and ALTLVDS_RX) IP Core User Guide". There's a bunch of example designs.

There is no guarantee that any of these examples is good, but at least its a start :)

Cheers,

Dave

Hi Dave

Hate to keep going around, I read the Clocks in Chapter 4 and I/O of chapter 5 in the Stratix V manual and I read the datasheet of Stratix V. then I read chapter 1 in LAB, ALM etc that I can have 2 4 input block, a 6 input block and all that. It absolutely did not answer any of my questions and concern. Yes, I learn there are GCLK, RCLK that divided into 4 quadrants, PCLK. I learn all the different standard of input by adjusting the VccIO and VCCPD etal. I learn there are different I/O bank like 3A, 3B, 7A........... I scanned through pages of the Arris II data sheet, same thing. I even scanned through the Stratix design guide.

My basic questions are very basic and simple that can help me in choosing the device:

1) What is Reference clock vs data rate in the I/O

2) Max clock frequency of simple basic FF and register.

3) Tpd from clock to Q.

4) Ts data setup time on D input to rising edge of clock( without worrying about the programmable delay line).

5) Th data hold time of D input from rising edge of clock( without worrying about the programmable delay line).

6) Tpd of simple AND, OR, NAND, NOR gate.

7) Are the FF/registers synchronous reset or level reset.

8) Do the FF/registers have clock enable.

These can be written in one short page and people will know exactly how to design the basic core elements. All you have to do is then talk about how to program to run the clock in GCLK, RCLK or PCLK to control skew and program the setup and hold time with the programmable delay. But the documentation rattling on for hundreds of pages.....................

As I said, I am no expert in FPGA programming. BUT I fixed enough problem left by the supposedly "FPGA engineer", people over threat programming FPGA like software programming. People seems to forget this is real hardware with wires, transistors. I had to fix FPGA programs in the pass written by some "FPGA engineers" on intermittent problems in the system that turn out to be the reset of the FF driven by combination logic. Totally ignore that these are really electrical signal that have propagation delay and can create glitches on the reset line during the transition of the input of the combination logic and reset the FF. This is such an obvious thing that the old school digital designer can spot in a seconds. Believe me, I caught multiple programs like this. fix these and the system became reliable. I can't help by vent the frustration in reading materials from Altera. My experience is the same when I went through MAX and APEX design. Just going around and around.

Sorry to vent.,

Alan.