Looking for FPGA that can have FF and shift register that can clock at 1GHz

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Hi Alan,

You have misunderstood. I was warning you that an FPGA expects a digital signal. Re-read my post. The digital signal requirements for LVDS and SERDES are that the signal amplitude be 350mVpp to 400mVpp. If your signals do not have many toggles, then they would also need to be DC coupled to the digital inputs, with an appropriate bias voltage applied.

Your signal *does not* meet these requirements, so you need to decide how you are going to interface your signal to the FPGA.

The board I provided a link to has a dual 1GHz ADC interfaced to an FPGA. The ADC is *not* part of the FPGA.

If you only care about the time at which your pulses occur, and not their amplitude, then you might be able to use a limiting amplifier with high gain, and then interface that to the FPGA inputs.

Cheers,

Dave

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Thanks

I already planned on having analog amplifier driving comparator to get the correct digital interface signal to drive the FPGA. If SERDES doesn't have the logic I want, then I am going to spend some time concentrate reading the Stratix V manual, datasheet for a while. From what I read your posts, sounds like Stratix V should work for me.

Does Altera have free simulation program?

Alan

Thanks

I already planned on having analog amplifier driving comparator to get the correct digital interface signal to drive the FPGA. If SERDES doesn't have the logic I want, then I am going to spend some time concentrate reading the Stratix V manual, datasheet for a while. From what I read your posts, sounds like Stratix V should work for me.

Does Altera have free simulation program?

Alan

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I already planned on having analog amplifier driving comparator to get the correct digital interface signal to drive the FPGA.

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Ok, that sounds good. Keep in mind that the comparator output should be differential, and if the signal needs to be DC coupled to the SERDES, you'll need to match the common-mode voltage of either the LVDS receiver or the SERDES receiver (see the data sheet for details).

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If SERDES doesn't have the logic I want, then I am going to spend some time concentrate reading the Stratix V manual, datasheet for a while. From what I read your posts, sounds like Stratix V should work for me.

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There are Cyclone and Arria devices with transceivers too. However, whatever you learn from reading the Stratix V manual will apply to them too, so start with the Stratix V manual.

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Does Altera have free simulation program?

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Yes. Altera supplies a version of Mentor Graphics Modelsim called Modelsim-ASE (Altera Starter Edition). Its good enough for what you want to look at. The main limitation is that it only handles one HDL language (easy enough to deal with) and its crippled, i.e., transceiver simulations take longer than they do in Modelsim-SE. In your case, free probably outweighs the cost of paying for Modelsim-SE :)

Cheers,

Dave

thanks

Is Quartus II similar to Quaretus I learned 10 years ago? They still using AHDL programming?

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Is Quartus II similar to Quartus I learned 10 years ago?

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I'm sure the interface has changed. Just go through a getting started tutorial and you'll get the hang of it.

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They still using AHDL programming?

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Its supported, but I would not recommend using it. Quartus supports both VHDL, Verilog, and SystemVerilog. Much of the latest IP is written using SystemVerilog. If you have to learn a language, I'd probably recommend looking at SystemVerilog ... but personally I use VHDL and SystemVerilog when needed, eg., when writing a tutorial that needs to use a single language simulator.

Here's a couple of documents that you can look at;

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

Look at the transceiver toolkit documents and the Altera JTAG-to-Avalon-MM tutorial.

Cheers,

Dave

Thanks Dave

I am reading the Stratix V manual, still on chapter 1!!!

Any suggestion on good link to learn VHDL?

Thanks

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I am reading the Stratix V manual, still on chapter 1!!!

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You should browse through it, but don't really bother "reading" it in-depth. Also browse through the Quartus II manual.

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Any suggestion on good link to learn VHDL?

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No, not a link. Go and buy a development board. The board does not even have to be suitable for your current project, eg., Arrow have a $30 board called the BeMicro-MAX10. Buy it. When it is sitting in your hand you'll have this overwhelming desire to make it work ... only then should you bother trying to read a handbook or learn an HDL language.

Look at the link I sent you above. There's plenty of HDL code associated with it - both VHDL and SystemVerilog. Use Google to learn the basics of the language. If you decide to get a book on VHDL, get Ashenden's book (The Designer's Guide to VHDL, 3rd Ed) ... but its probably not the best book to learn with ...

You can also use Quartus II to learn an HDL. The help menu has links to tutorials. The Altera University Program web site has lots of tutorials. The Quartus II editor has templates for VHDL, Verilog, etc.

Cheers,

Dave

OK thanks

I was really reading the manual!!! Like how many inputs, register, internal clks and all!!! I never read in detail when I did the other designs because I was not pushing the speed, I thought I need to read in detail so I know how to control the path to achieve the 1GHz clocking.

OK I just go through it faster.

Thanks

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I was really reading the manual!!! Like how many inputs, register, internal clks and all!!!

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Its good to get an idea of the resources, but in your case, your design is small relative to pretty much any FPGA. Your primary objective is to get your head around what FPGAs can do, and then see how you can apply it to your design.

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I never read in detail when I did the other designs because I was not pushing the speed, I thought I need to read in detail so I know how to control the path to achieve the 1GHz clocking.

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There is no problem creating an LVDS or SERDES interface at 1GHz. The bigger question for you, is "Is that suitable for your application?"

You can read the digitizer document here;

https://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf

It has details on tests of the LVDS at 1GHz, eg., see p64. The LVDS interface is the *digital* link between the ADC and the FPGA. It can be operated as 8-bits at 1GHz or 16-bits at 500MHz. The hardware design supports both schemes.

Cheers,

Dave

Am I reading wrong or one of these FPGA is over $2000?

If so, that's too high for my design. Is there any older FPGA that can still work for my requirements?

Thanks