Long counter (30s) in VHDL, balancing a clock divide and counter size

If you need just a fixed duration counter (ie, don't need to load arbitrary count values) I would examine use of an LFSR approach to use a minimal number of cells. The number of cells will basically track the length of the counter. A 30 bit counter could have a period of 2^30-1 clocks (this is what is know as a maximal length LFSR). Here is a good quick reference: https://en.wikipedia.org/wiki/Linear-feedback_shift_register