Forum Discussion

RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
5 years ago

Logic tree evaluation VHDL Max10

Hello not sure to place question here or on Quartus. I got back and try'd again latest release, so a great doubt it is time to retirement? [noob mode on] How to evaluate these small vhdl snipp...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
5 years ago

Hello, I am completing port to Xilinx Spartan, to do so I teared down all QSYS logic and rewrote some part of IP core.

It is no more using Avalon is not supported on, use instead native block, it seems not suffering none of issue experienced. The one are here are justified I don't know about, Its since long long time I migrated to Altera, Xilinx and Lattice too changed a lot and actual family are new to me.

I am rewriting IP as platform/vendor neutral to isolate issue. Actual issue are not similar to what I encountered on MAX10, just fresh code is not as clean as the old one used for years no more Avalon/Qsys oriented.

Think it took few day more to complete.