Forum Discussion

RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
5 years ago

Logic tree evaluation VHDL Max10

Hello not sure to place question here or on Quartus. I got back and try'd again latest release, so a great doubt it is time to retirement? [noob mode on] How to evaluate these small vhdl snipp...
  • RRomano001's avatar
    RRomano001
    Icon for Contributor rankContributor
    5 years ago

    Hi, I bought too many MAX10 part and board. I don't need manufacture more board costed a fortune and time none never pay for.

    If you send me a private address I can send DE10-lite hosted design.

    Plot of issue is present on files in zip, T80 Avalon has a MOORE automata clocked to 100MHz Avalon, cannot stay in initial state, must evolve to idle adsorbing or waiting on T2, so issue is unclear to me...

    Again Wait state both used to T80 core (Free IP core), on LA mapping appear polarity reversed.

    When wait signal driven to '1' what is on output? Why output appear so weird than '1' as expected to be?

    No I don't buy nothing more.