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RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
5 years ago

Logic tree evaluation VHDL Max10

Hello not sure to place question here or on Quartus. I got back and try'd again latest release, so a great doubt it is time to retirement? [noob mode on] How to evaluate these small vhdl snipp...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


There are some missing files in the ZIP file.


Warning (12019): Can't analyze file -- file Z80test_LCD_NoNios_Debug/synthesis/Z80test_LCD_NoNios_Debug.vhd is missing

Warning (12019): Can't analyze file -- file ../../my_Core/Protti_PP52/Z80_ROM_MMU_ver1_02.vhd is missing

Warning (12019): Can't analyze file -- file ../../my_Core/T80/T80avalon_006.vhd is missing


Could you provide the design QAR file by clicking on Project > Archive Project > Archive


Thanks

Best regards,

KhaiY


RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
5 years ago

Hi, I can send in NDA form, this way cannot publish here.

Custom board is SRAM based, LCD IPCORE fail an odd way. Ethernet added to inspect, core failed too on combinatorial terms. This scared me a lot about possible pattern sensitivity or software degrade.

Test (2018) was to add T80 core and see if LCD work. Some core got imported from Xilinx part or GAL where they run fine.

Suspended development for a long while....

Seen version 2020, last try was on Lite-10 board, LCD must be wired up to. After no success on I am porting to Xilinx Spartan-6 board to see what happen.

Max10 family appeared as best fit and secure way but Altera was no more Altera.