Logic family for REFCLK

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For a new design we need to provide a 150MHz REFCLK to a set of Cyclone V transceivers. The oscillator output will only drive the REFCLK inputs. My question is which logic family I should use for the oscillator.

LVDS looks like the simplest one with no external termination. The oscillator will be located very close to the FPGA, just on the opposite side of the board from it.

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You need to read the handbook. You need to check the receiver common-mode value and the peak-to-peak voltage swing is compatible. If the common-mode is not compatible, then you can AC-couple the external clock source to the REFCLK pin.

Using a differential LVDS clock with AC coupling is likely to be your best option (since you can always load the AC coupling capacitor pads with resistors if you really need a DC connection).

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VCC_FPLL = VCCH_GXBL = 2.5V. Does that mean a 2.5V oscillator is required, or may a 3.3V part be used?

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This is not the parameter to check to determine the logic compatibility of the REFCLK signal.

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A related question is wheter or not I can tap the 150MHz signal into the FPGA's core. Is it possible to route the same clock to PLLs related to transceivers, AND use it to run the main application in the core? We hope to avoid clock distribution chips outside the FPGA IC.

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I'm not sure if this applies to the Cyclone V, but it does on the Cyclone IV and Stratix IV, if you do not have a transceiver block instantiated in your design, then you cannot use the REFCLK pins associated with that block. So, this means you need to use an external fanout device to send the clock source to both REFCLK and CLKIN pins on the FPGA.

I've been looking at parts for a 10Gbps link REFCLK source. SiLabs recommended I look at the SiLabs Si5368 for the REFCLK and the Si5338 for other general purpose clocks. I haven't looked at detail in those data sheet yet, but perhaps they'll work for your application too. The nice thing about using something like the Si5368 is that you can use a range of reference frequencies and produce a range of REFCLK frequencies. This can be useful if the FPGA PLL feedback dividers don't quite have enough options.

Cheers,

Dave

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We have successfully driven REFCLK pins to PLLs, generated our frequency for user logic AND Serdes' refclk ports in arria v. I suspect you can do the same for CV. We used lvds or lvpecl. AC coupling's the most important part

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Are you able to use the REFCLK pin if you do not instantiate a SerDes block? I haven't tried this with any of the V series devices, but its not possible with the IV series. The work-around is to create an ALTGX+ALTGX_RECONFIG component, and then essentially not use it (reset it).

Cheers,

Dave

I have not tried it in S4 because we use the clkin_50 port on the S4 kit (instead of a refclk port). I have used one of the refclk pins in the A5 kit because I needed to use an SMA driven clock for a while. Never tried either without a transceiver.

The trick with A5 was to use an altclkctrl like so:

altclkctrl# (

.clock_type("GLOBAL CLOCK"),

.number_of_clocks(1)

) global_pll_ref_clk_inst (

.inclk(REFCLK_P),

.outclk(REFCLK_P_BUF)

);

and drive REFCLK_P_BUF to the pll input, and REFCLK_P to the transceiver.

So I guess it is slightly different than I had originally explained

Our Stratix V design does use a PLL output to the transceiver, but thats a whole different beast

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Never tried either without a transceiver.

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Ok, thanks!

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The trick with A5 was to use an altclkctrl

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Thanks for the hint, I'll have to try a few more tests when I get some time.

Cheers,

Dave