Logic family for REFCLK

I have not tried it in S4 because we use the clkin_50 port on the S4 kit (instead of a refclk port). I have used one of the refclk pins in the A5 kit because I needed to use an SMA driven clock for a while. Never tried either without a transceiver.

The trick with A5 was to use an altclkctrl like so:

altclkctrl# (

.clock_type("GLOBAL CLOCK"),

.number_of_clocks(1)

) global_pll_ref_clk_inst (

.inclk(REFCLK_P),

.outclk(REFCLK_P_BUF)

);

and drive REFCLK_P_BUF to the pll input, and REFCLK_P to the transceiver.

So I guess it is slightly different than I had originally explained

Our Stratix V design does use a PLL output to the transceiver, but thats a whole different beast